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Memory architecture
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201	spcl.inf.ethz.ch @spcl_eth S. DI GIROLAMO, P. JOLIVET, K. D. UNDERWOOD, T. HOEFLER Exploiting Offload Enabled Network Interfaces Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-09-01 08:50:16 Computing Computer memory Remote direct memory access Lossless compression Computer architecture Computer hardware Networking hardware Ethernet
202	Notified Access: Extending Remote Memory Access Programming Models for Producer-Consumer Synchronization Roberto Belli, Torsten Hoefler Dept. of Computer Science, ETH Zurich {bellir,htor}@inf.ethz.ch Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-02-28 04:22:06 Computing Concurrent computing Computer programming Parallel computing Inter-process communication Application programming interfaces Concurrency Message Passing Interface Distributed computing architecture SHMEM Message queue Synchronization
203	Virtual Memory Architecture in SunOS Robert A. Gingell Joseph P. Moran William A. Shannon Sun Microsystems, IncGarcia Ave. Add to Reading List Source URL: kos.enix.org Language: English - Date: 2001-06-12 15:33:28
204	A Heap of Trouble Exploiting the Linux Kernel SLOB Allocator Dan Rosenberg Add to Reading List Source URL: vulnfactory.org Language: English - Date: 2012-01-14 17:26:28 Computer architecture Software Linux kernel Computing SLOB SLUB Slab allocation Heap overflow C dynamic memory allocation Memory management Kernel
205	Technical Report UCAM-CL-TR-579 ISSNNumber 579 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2004-02-13 14:20:06 Concurrency control Computing Data management Computer architecture Non-blocking algorithm Lock Mutual exclusion Linearizability Readerswriter lock Synchronization Software transactional memory Memory barrier
206	Opportunities for Parallelism in Matrix Multiplication FLAME Working Note #71 Tyler M. Smith∗ Robert A. van de Geijn∗ Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2014-01-10 19:11:37 Parallel computing Compiler optimizations Computer architecture CPU cache Central processing unit Computer memory Xeon Automatic parallelization Basic Linear Algebra Subprograms Nehalem Thread
207	Active Access: A Mechanism for High-Performance Distributed Data-Centric Computations Maciej Besta Torsten Hoefler Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-04-19 21:19:08 Computing Computer hardware Computer architecture Memory management Virtual memory Computer memory Inputoutput memory management unit X86 virtualization Direct memory access Shared memory Remote direct memory access Translation lookaside buffer
208	ARTIK Family Overview ARTIK is a family of modules (ARTIK 1, ARTIK 5, ARTIK 10) tailored for the Internet of Things (IoT). With a tiered architecture built for performance, optimized power consumption, and memory Add to Reading List Source URL: static.artik.io Language: English - Date: 2015-10-27 19:50:26
209	a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus and Dual Data Buses Add to Reading List Source URL: www.uhf-satcom.com Language: English - Date: 2007-07-28 07:54:40
210	Anatomy of High-Performance Many-Threaded Matrix Multiplication Tyler M. Smith∗ , Robert van de Geijn∗ , Mikhail Smelyanskiy† , Jeff R. Hammond‡ and Field G. Van Zee∗ ∗ Institute for Computational Engineerin Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2014-02-10 15:58:29 Computer architecture Parallel computing Compiler optimizations Cache Computer memory CPU cache Xeon Phi Multi-core processor Xeon Loop nest optimization Nehalem PowerPC A2

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